Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB 2.0 Full High Speed Solution | NXP Semiconductors
76892 - Versal: MIO USB 2.0 Interfaces
USB2 PHY | Cadence
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
XPS USB 2.0 Host Controller
USB3280 | Microchip Technology
USB 2.0 PHY Verification
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB2 Controller | Cadence
TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
PCIe/USB/SATA PHY Appilcation example | Renesas
USB v2.0 Soft PHY and Device Controller
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Full Speed USB 2.0 Hub Controller - EEWeb
OpenFive-USB IP Subsystem-USB 3.1 Controller-USB 3.2 Retimer
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
TUSB1210 data sheet, product information and support | TI.com
USB Universal Serial Bus
USB 2.0 Full High Speed Solution | NXP Semiconductors
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
The Next-Generation Interconnect | Mouser
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
USB 2.0 PHY for SoC Designs | Cadence IP
